In the semiconductor integrated circuit (IC) industry, technological advances in IC materials and design have produced generations of ICs where each generation has smaller and more complex circuits than the previous generation. In the course of IC evolution, functional density (i.e., the number of interconnected devices per chip area) has generally increased while geometry size (i.e., the smallest component (or line) that can be created using a fabrication process) has decreased. This scaling down process generally provides benefits by increasing production efficiency and lowering associated costs. Such scaling down has also increased the complexity of IC processing and manufacturing.
One type of component in an integrated circuit is a nanowire. A nanowire is an elongated semiconductor structure that may be used as part of a transistor. Specifically, portions of the nanowire may be doped to form source and drain regions. Additionally, a gate layer may be formed such that it wraps around the nanowire over a channel region between the source and drain regions of the nanowire.
Nanowires may be formed in a variety of ways. Typically, a nanowire is grown using an epitaxial process. Generally, a single epitaxial process is used to grow multiple nanowires at the same time. But, due to various process characteristics, each of the nanowires may not be the same height after the epitaxial process is complete. For better device operation, it is desirable that such nanowires have a substantially similar height.